Array mapping in behavioral synthesis

Author

Schmit, Herman ; Thomas, Donald E.

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

fYear

1995

fDate

13-15 Sep 1995

Firstpage

90

Lastpage

95

Abstract

This paper discusses the mapping of arrays in a behavior to memories in an implementation. We introduce a design representation based on a variety of array grouping techniques and the binding of array groups to memory components with different dimensions, access times, and number of ports. The results of design actions are computed in terms of the number of memory components and the length of schedules in the behavior. We demonstrate the ability of a synthesis tool using this representation to generate designs that span the entire range of the memory design space

Keywords

data structures; hardware description languages; memory architecture; scheduling; access times; array grouping; array mapping; behavioral synthesis; binding; design representation; hardware synthesis; memory architecture; memory components; memory design space; schedule length; synthesis tool; Costs; Data structures; Digital signal processing; Hardware; Law; Legal factors; Memory architecture; Random access memory; Simultaneous localization and mapping; Specification languages;

fLanguage

English

Publisher

ieee

Conference_Titel

System Synthesis, 1995., Proceedings of the Eighth International Symposium on

Conference_Location

Cannes

ISSN

1080-1820

Print_ISBN

0-8186-7076-2

Type

conf

DOI

10.1109/ISSS.1995.520618

Filename

520618