Cell selection from technology libraries for minimizing power

Author

Zhang, Yumin ; Xiaobo Hu ; Chen, Hu Danny Z

Author_Institution

Synopsys Inc., Mountain View, CA, USA

fYear

2001

fDate

2001

Firstpage

609

Lastpage

614

Abstract

In this paper we present a new library-oriented cell selection approach to minimize power consumption of combinational circuits. Our unified mixed integer-linear-programming (MILP) formulation selects library cells with different gate sizes, supply voltages and threshold voltages simultaneously during technology mapping. Experimental results on benchmarks mapped to an industrial library show that our technique achieves 19% more power saving in less CPU time comparing with other approaches

Keywords

CMOS logic circuits; cellular arrays; circuit complexity; combinational circuits; integer programming; linear programming; logic CAD; low-power electronics; minimisation of switching nets; CMOS library; combinational circuits; delay differences; library-oriented cell selection; logic synthesis; low power cell selection; pin variance; power consumption minimization; standard cell design; technology mapping; unified mixed integer-linear-programming formulation; Capacitance; Combinational circuits; Computer science; Delay; Energy consumption; Libraries; Power engineering and energy; Simultaneous localization and mapping; Threshold voltage; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific

Conference_Location

Yokohama

Print_ISBN

0-7803-6633-6

Type

conf

DOI

10.1109/ASPDAC.2001.913376

Filename

913376