A DSP-based ramp test for on-chip high-resolution ADC

Ramp test approach is widely used in analog-to-digital converter (ADC) built-in self-test (BIST), which generates linear and slow-slope analog ramp signals intended for histogram-based non-linearity test. The test time can be high for high-resolution ADCs. In this paper, a new DSP-based ramp test approach is presented to address the test time issue. The linear range of signal ramp is divided into two parts and a sum of measured ADC outputs is calculated in each part. Characteristics of ramp signals are derived from the two sums so that time-domain function of the ramp generator can be approximately reconstructed to determine non-linearity error of each ADC measurement. With the obtained testing signal function, non-linearity of each measured code is obtained. A minimal number of samples is required to make sure that quantization errors and the non-linearity of unmeasured code are acceptable. Simulations show that the proposed approach is suitable for quick static test of most on-chip high-resolution ADCs.