DocumentCode
2995187
Title
An improved configurable 2-D linear feedback shift register for embedded core built-in self-test
Author
Vemuru, Srinivasa ; Kristem, Sravani ; Niamat, Mohammed
Author_Institution
Dept. of Electr. & Comput. Eng. & Comput. Sci., Ohio Northern Univ., Ada, OK, USA
fYear
2011
fDate
14-16 March 2011
Firstpage
208
Lastpage
213
Abstract
This paper presents an optimization scheme for the synthesis of built-in self-test circuitry for embedded cores. This scheme is based on a two dimensional linear feedback shift registers that make use of XOR and XNOR gates. The proposed scheme results in configuration networks with up to 33% reduction in XOR gate inputs and up to 25% reduction in transistor count as compared to prior work in 2-D linear feedback shift registers.
Keywords
built-in self test; circuit feedback; circuit optimisation; embedded systems; logic gates; shift registers; transistor circuits; 2D linear feedback shift registers; XNOR gates; XOR gates; built-in self-test circuitry; configurable 2D linear feedback shift register; configuration networks; embedded core built-in self-test; optimization scheme; transistor count; two dimensional linear feedback shift registers; Arrays; Benchmark testing; Flip-flops; Inverters; Logic gates; Shift registers; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
System Theory (SSST), 2011 IEEE 43rd Southeastern Symposium on
Conference_Location
Auburn, AL
ISSN
0094-2898
Print_ISBN
978-1-4244-9594-8
Type
conf
DOI
10.1109/SSST.2011.5753808
Filename
5753808
Link To Document