Title :
Effectiveness of the ASIP design system PEAS-III in design of pipelined processors
Author :
Kitajima, Akira ; Itoh, Makiko ; Sato, Jun ; Shiomi, Akichika ; Takeuchi, Yoshio ; Imai, Masaharu
Author_Institution :
Dept. of Inf. & Math. Sci., Osaka Univ., Japan
Abstract :
In this paper, the effectiveness of the ASIP (Application Specific Instruction set Processor) design system PEAS-III is evaluated through experiments. Examples in experiments are a MIPS R3000 compatible processor, DLX, a simple RISC controller, and PEAS-I core. While they are simple in-order pipelined processors, they have enough facilities for real embedded system design. Through experiments, easiness of design and modification for improvement and design quality in terms of performance and hardware cost are discussed. It has been confirmed that the design method used in PEAS-III is effective to design space exploration for simple pipelined processors
Keywords :
application specific integrated circuits; embedded systems; integrated circuit design; microcontrollers; microprocessor chips; pipeline processing; reduced instruction set computing; ASIP design; DLX; MIPS R3000 compatible processor; PEAS-I; PEAS-III; RISC controller; application specific instruction set processor; embedded system; pipelined processor; Application specific processors; Costs; Embedded system; Hardware; Informatics; Pipeline processing; Process design; Reduced instruction set computing; Space exploration; System-on-a-chip;
Conference_Titel :
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-6633-6
DOI :
10.1109/ASPDAC.2001.913383
