DocumentCode :
2995275
Title :
High-level specification and efficient implementation of pipelined circuits
Author :
Marinescu, Maria-Cristina ; Rinard, Martin
Author_Institution :
Lab. for Comput. Sci., MIT, Cambridge, MA, USA
fYear :
2001
fDate :
2001
Firstpage :
655
Lastpage :
661
Abstract :
This paper describes a novel approach to high-level synthesis of complex pipelined circuits, including pipelined circuits with feedback. This approach combines a high-level, modular specification language with an efficient implementation. In our system, the designer specifies the circuit as a set of independent modules connected by conceptually unbounded queues. Our synthesis algorithm automatically transforms this modular, asynchronous specification into a tightly coupled, fully synchronous implementation in synthesizable Verilog
Keywords :
circuit feedback; hardware description languages; high level synthesis; pipeline processing; Verilog algorithm; feedback; hardware design; high-level synthesis; modular specification language; pipelined circuit; Circuit synthesis; Clocks; Computer science; Coupling circuits; Feedback circuits; Hardware design languages; Laboratories; Pipeline processing; Scheduling algorithm; Specification languages;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2001. Proceedings of the ASP-DAC 2001. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-6633-6
Type :
conf
DOI :
10.1109/ASPDAC.2001.913384
Filename :
913384
Link To Document :
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