Weighted bridging fault coverage using capacitance extraction

In this paper we discuss the efficiency and accuracy of extracting potential bridging fault sites from a physical layout specification. Using a combination of developed tools and common layout and extraction tools, a fault file is generated with an ordered list of the most likely to occur bridging faults based on parasitic capacitance values. These faultsare then simulated and results are discussed. Using this method and the tools created, the efficiency and accuracy of simulating bridging faults can be greatly improved. This process was implemented for multiple circuits using a newly developed general purpose fault extraction tool.