Title :
Merged scaling multiplication CORDIC algorithm
Author :
Wang, Shaoyun ; Piuri, Vincenzo ; Swartzlander, Earl E., Jr.
Author_Institution :
Crystal Semicond. Corp., Austin, TX, USA
Abstract :
In an N-bit fixed-point processor, the COordinate Rotation DIgital Computer (CORDIC) algorithm usually consists of N elementary iterations and one scaling multiplication. For the constant scale factor algorithm, we propose a new approach that merges the iterations with the scaling to achieve a more regular and pipelinable structure of the processor, which is well suited for VLSI implementation
Keywords :
VLSI; algorithm theory; digital arithmetic; iterative methods; pipeline arithmetic; VLSI implementation; constant scale factor algorithm; fixed-point processor; iterations; merged scaling multiplication CORDIC algorithm; pipelinable structure; Application software; Arithmetic; Clocks; Complexity theory; Computer applications; Control system synthesis; Iterative algorithms; Signal processing algorithms; Throughput; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.612852
