Title :
Don´t care minimization of multi-level sequential logic networks
Author :
Lin, B. ; Touati, H.J. ; Newton, A.R.
Author_Institution :
California Univ., Berkeley, CA, USA
Abstract :
The authors address the problem of computing sequential don´t cares that arise in the context of multi-level sequential networks and their use in sequential logic synthesis. The key to their approach is the use of binary decision diagram (BDD)-based implicit state space enumeration techniques and multi-level combinational simplification procedures. Using the algorithms described, exact sequential don´t care sets for circuits with over 10/sup 68/ states have been successfully computed.<>
Keywords :
logic CAD; sequential circuits; binary decision diagram; combinational simplification; don´t care minimisation; multilevel sequential logic networks; sequential logic synthesis; state space enumeration; Automata; Boolean functions; Computer networks; Data structures; Logic; Minimization; Network synthesis; Sequential circuits; State-space methods; Testing;
Conference_Titel :
Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2055-2
DOI :
10.1109/ICCAD.1990.129940
