Don´t care minimization of multi-level sequential logic networks

The authors address the problem of computing sequential don´t cares that arise in the context of multi-level sequential networks and their use in sequential logic synthesis. The key to their approach is the use of binary decision diagram (BDD)-based implicit state space enumeration techniques and multi-level combinational simplification procedures. Using the algorithms described, exact sequential don´t care sets for circuits with over 10/sup 68/ states have been successfully computed.<>