An Energy-Efficient Differential Flip-Flop for Deeply Pipelined Systems

Deeply pipelined systems require flip-flops with low latency and power consumption. Often, the flip-flop must supply both inverted and non-inverted signals to subsequent logic. Generating both outputs at the same time improves performance by equalizing the worst-case delays. In this paper, we present a novel differential flip-flop for deeply pipelined systems. The circuit uses cross-coupled p-transistors as pull-up devices to achieve high energy efficiency. We simulated the design in 90-nm CMOS technology to determine the delay and power consumption. We then repeated the analysis with four other differential flip-flops that produce symmetric outputs. The proposed design achieves the best power-delay product of the five alternatives.