Truncated multiplication with correction constant [for DSP]

Multiplication is frequently required in digital signal processing. Parallel multipliers provide a high-speed method for multiplication, but require large area for VLSI implementations. In most signal processing applications, a rounded product is desired to avoid growth in word-size. Thus an important design goal is to reduce the area requirements of rounded output multipliers. The authors present a technique for parallel multiplication which computes the product of two numbers by summing only the most significant columns of the multiplication matrix, along with a correction constant. A method for selecting the value of the correction constant which minimizes the average and mean square error is introduced. Equations are given for estimating the average, mean square, and maximum error of the rounded product. With this technique, the hardware requirements of the multiplier can be reduced by 25 to 35%, while limiting the maximum error of the rounded product to less than one unit in the last place