A clock net reassignment algorithm using Voronoi diagram

A novel algorithm is presented for the clock net reassignment problem in semi-custom layout design. The clock net reassignment is used to shorten clock nets by reconnecting clock drivers and flip-flops so as to obtain high performance LSIs. The proposed algorithm, by using the Voronoi diagram in computational geometry, is quite efficient and gives better assignments than existing techniques. The experimental results show that the algorithm yields a 10% reduction in net lengths in comparison with existing algorithms. The algorithm takes only 18 s to find an assignment for 167 drivers and 833 flip-flops.<>