Reliability impacts of multiple-bit-per-chip RAMs

The author considers the need to use error-correcting codes which have the same efficiency of the traditional single-bit-error-correcting and double-bit-error-detecting (SBEC-DBED) codes but which can be used with the current multiple-bit-per-chip organizations. A short summary is presented of memory chip and memory card configurations along with common chip failure modes and how SBEC-DBED and DBEC-TBED (double-bit-error-correcting-triple-bit-error-detecting) error-correcting codes are used to overcome these failures. This is followed by a description of the problem with the use of multiple-bit-per-chip organizations. Solutions that would satisfy the reliability requirements are included