Title :
A unified systolic design technique based on integral matrix theory
Author :
Lorenzelli, F. ; Yao, K.
Author_Institution :
Electr. Eng. Dept., UCLA, Los Angeles, CA, USA
Abstract :
A systematic mapping procedure for systolic arrays is considered. Integral matrix theory provides the basic concepts used to define projection and scheduling vectors. Unimodular matrices are defined which describe projection, timing, and bases for the processor space and the isochronous hyperplanes. The same mathematical tools furnish the rigorous definition of the partitioning block structure, as well as the cluster set. Folding and design constraints can also be included, and are briefly considered. The possible application of a systolic design for low power requirements is also discussed
Keywords :
CMOS digital integrated circuits; VLSI; digital signal processing chips; logic partitioning; matrix algebra; parallel algorithms; pipeline processing; scheduling; systolic arrays; timing; CMOS; VLSI; bases; cluster set; design constraints; folding constraints; integral matrix theory; isochronous hyperplanes; low power requirements; partitioning block structure; pipelined architecture; processor space; projection; scheduling vectors; signal processing; systematic mapping procedure; systolic arrays; timing; unified systolic design technique; unimodular matrices; Concurrent computing; Integral equations; Parallel architectures; Parallel processing; Processor scheduling; Signal design; Systolic arrays; Throughput; Timing; Very large scale integration;
Conference_Titel :
VLSI Signal Processing, VI, 1993., [Workshop on]
Conference_Location :
Veldhoven
Print_ISBN :
0-7803-0996-0
DOI :
10.1109/VLSISP.1993.404469
