Title :
System-MSPA design of H.263+ video encoder LSI for face focused videotelephony
Author :
Honsawek, Chawalit ; Ito, Kazuhito ; Ohtsuka, Toshiyuki ; Isshiki, Tsuyoshi ; Li, Dongju ; Adiono, Trio ; Kunieda, Hiroaki
Author_Institution :
Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
Abstract :
In this paper, an LSI design for video encoder and decoder for H.263+ video compression with object based coding is presented. LSI operates under clock frequency of 27 MHz to compress QCIF(176×144 pixels) at the frame rate of 30 PB-frame per second. The core size is 4.5×4.5 mm2 in a 0.35 μm process. The architecture is based on bus connected heterogeneous dedicated modules, named as system MSPA architecture. It employs fast and small-chip-area dedicated modules in lower level and controls them by employing the slow and flexible programmable device and an external DRAM. Design results achieve real time encoder in quite a compact size without losing flexibility and expandability. Real time emulation and easy test capability with external PC is also implemented
Keywords :
data compression; large scale integration; video codecs; video coding; videotelephony; 0.35 micron; 27 MHz; H.263+ video encoder LSI; bus connected heterogeneous dedicated modules; clock frequency; core size; external DRAM; face focused videotelephony; flexible programmable device; frame rate; object based coding; real time emulation; system-MSPA design; test capability; video compression; Algorithm design and analysis; Clocks; Decoding; Delay; Large scale integration; Motion estimation; Random access memory; Testing; Video coding; Video compression;
Conference_Titel :
Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on
Conference_Location :
Tianjin
Print_ISBN :
0-7803-6253-5
DOI :
10.1109/APCCAS.2000.913429
