• DocumentCode
    2996165
  • Title

    Behavior Aware Data Locality for Caches

  • Author

    Gangyong Jia ; Xi Li ; Chao Wang ; Xuehai Zhou ; Zongwei Zhu

  • Author_Institution
    Dept. of Comput. Sci. & Technol., Univ. of Sci. & Technol. of China (USTC), Hefei, China
  • fYear
    2012
  • fDate
    17-19 Dec. 2012
  • Firstpage
    514
  • Lastpage
    521
  • Abstract
    Optimizing cache performance through improving data locality has been receiving a lot of attention. However, none of the existing approaches can combine each task´s behavior to optimize data locality for caches. We present a behavior aware data locality (BADL) to optimize cache performance in this paper. The key idea is to add each task´s behavior when allocating memory, which can take advantage of each task´s different locality to optimize cache performance. There are five main contributions: 1. to our best knowledge, this is the first attempt to improve cache performance through combining task behavior, 2. BADL detailed analyzes low performance derived from internal of the cache line, which is more fine-grained than the current state-of-the-art fine-grained in hardware angle, 3. BADL optimizes the cache performance through improving internal of cache line efficiency, 4. we implement BADL both in single-threaded application and multi-threaded applications scenarios, 5. BADL can be combined to most of the cache optimizing researches. The experiment results show our proposed BADL can improve 18.6% performance on average in single-threaded application situation and improve 20.8% performance on average in multi-threaded application situation.
  • Keywords
    cache storage; data handling; multi-threading; software performance evaluation; storage allocation; BADL; behavior aware data locality; cache performance optimization; hardware angle; internal cache line efficiency improvement; memory allocation; multithreaded application situation; single-threaded application situation; task behavior; Benchmark testing; Distributed databases; Electronics packaging; Hardware; Instruction sets; Time frequency analysis; Cache performance; cache line; data locality; fine-grained; multi-threaded; single-threaded; task behavior;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Systems (ICPADS), 2012 IEEE 18th International Conference on
  • Conference_Location
    Singapore
  • ISSN
    1521-9097
  • Print_ISBN
    978-1-4673-4565-1
  • Electronic_ISBN
    1521-9097
  • Type

    conf

  • DOI
    10.1109/ICPADS.2012.76
  • Filename
    6414451