On computing the 2-D modulated lapped transform in real-time [and VLSI implementation]

The Lapped Orthogonal Transforms have successfully been used in image coding and motion estimation since they alleviate the blocking effect, common in transform domain techniques. The authors consider the hardware implementation of the two-dimensional Modulated Lapped Transform. A time-recursive approach in algorithm design is adopted that yields a modular, regular, highly parallel architecture requiring local communication. Overall, the architecture proposed for the N × N MLT requires O(N) processing elements, O(N²) storage elements and can be realized very efficiently in VLSI. Moreover, there is no restriction on N. Being fully pipelined this architecture may achieve the throughput rate of N cycles per N × N successive input data frame, and thus it is suitable for real time computation of the 2-D MLT