Optimizing Scheduling in Embedded CMP Systems with Phase Change Memory

Phase Change Memory (PCM) is emerging as one of the most promising alternative technology to the Dynamic RAM (DRAM) when building large-scale main memory systems. Even though the PCM is easy to scale, it encounters serious endurance problems. Writes are the primary wear mechanism in the PCM. The PCM can perform 10⁸ to 10⁹ times of writes before it cannot be programmed reliably. In addition, the PCM has high write latency. To prolong the lifetime of the PCM as the main memory and enhance the performance, we propose a Scratch Pad Memory (SPM) based memory mechanism and an Integer Linear Programming (ILP) memory activities scheduling algorithm to reduce the redundant write operations in the PCM. The idea of our approach is to share the data copies among the SPMs, instead of writing back to the PCM main memory each time a modify occurs. Our experimental results show that the ILP scheduling can generate the optimal schedule of memory activities with minimum write operations, reducing the number of write by up to 61%.