Power analysis of hardware based motion estimation in a heterogeneous reconfigurable environment

Motion estimation is the most computationally demanding task in MPEG-4 based video compression techniques. Motion estimation consumes 70% of the computational capability and its hardware realization contributes up to 60% of chip power. This paper describes our efforts in analyzing power consumption of motion estimation in custom VLSI architecture prototyped as a configurable system on a chip (CSoC). This CSoC exploits dynamic partial reconfiguration of FPGA to allow changing search techniques/ search area to facilitate efficient intermode decision. Dynamic partial reconfiguration adds flexibility in terms of chip area at the cost of overhead in time to reconfigure and extra power consumption during dynamic partial reconfiguration. We perform power analysis on hardware by taking configuration and hardware execution power into account and observe how frequency of partial reconfiguration affects net power consumption.