X-architecture clock tree construction associated with buffer insertion and sizing

Due to the advanced lithography technologies in current semiconductor process, X-architecture has been widely used in VLSI physical design. The architecture contributes more improvements in clock delay, wire length, and power consumption than those of Manhattan architecture. This work proposed an X-architecture zero skew clock tree construction with buffer insertion and sizing. A pattern matching method for paired points is applied to determine tapping points and simplify the merging procedure of DME approach. Next, Two unit-size buffers are respectively inserted into two branches of a tapping point and then the sizes of buffers are adjusted to minimize two branch delays. Moreover, X-flip and wire sizing techniques are sequentially applied to shorten wire length and keep zero skew. Given a set of n clock sinks and a B-type buffer library, the proposed algorithm can obtain a buffered X-architecture zero skew clock tree with minimal delay and power consumption in O(B²nlogn). Experimental results on benchmarks compared with other bufferless X-routing algorithms show the improvements of 98.9%, 1.4%, 90.2%, and 90.2% in terms of clock delay, wire length, downstream capacitance, and power consumption, respectively.