An Architecture for Reconfigurable Multi-core Explorations

Author

Serres, Olivier ; Narayana, Vikram K. ; El-Ghazawi, Tarek

Author_Institution

Dept. of Electr. & Comput. Eng., George Washington Univ., Washington, DC, USA

fYear

2011

fDate

Nov. 30 2011-Dec. 2 2011

Firstpage

105

Lastpage

110

Abstract

Multi-core systems are now the norm, and reconfigurable systems have shown substantial benefits over general purpose ones. This paper presents a combination of the two: a fully featured reconfigurable multi-core processor based on the Leon3 processor. The platform has important features like cache coherency, a fully running modern OS (GNU/Linux) and each core has a tightly coupled reconfigurable coprocessor unit attached. This allows the SPARC instruction set to be extended for the running application. The multi-core reconfigurable processor architecture, including the coprocessor interface, the ICAP controller and the Linux kernel driver, is presented. The experimental results show the characteristics of the platform including: area costs, the memory contention, the reprogramming cost. Speedups up to 100x are demonstrated on a cryptography test.

Keywords

Linux; cache storage; coprocessors; multiprocessing systems; reconfigurable architectures; ICAP controller; Leon3 processor; Linux kernel driver; SPARC instruction set; cache coherency; coprocessor interface; multicore reconfigurable processor architecture; multicore system; reconfigurable multicore exploration; reconfigurable multicore processor; reconfigurable system; Coprocessors; Encryption; Kernel; Linux; Multicore processing; Pipelines; Random access memory; multi-core; partial reconfiguration; reconfigurable processor;

fLanguage

English

Publisher

ieee

Conference_Titel

Reconfigurable Computing and FPGAs (ReConFig), 2011 International Conference on

Conference_Location

Cancun

Print_ISBN

978-1-4577-1734-5

Type

conf

DOI

10.1109/ReConFig.2011.10

Filename

6128562