• DocumentCode
    2996302
  • Title

    A Method for improved final placement employing branch-and-bound with hierarchical placement encoding and tightened bounds

  • Author

    Li, Xitian ; Lillis, John

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Illinois at Chicago, Chicago, IL, USA
  • fYear
    2009
  • fDate
    15-16 July 2009
  • Firstpage
    304
  • Lastpage
    312
  • Abstract
    A new method employing branch-and-bound for improved final placement is presented for the final step of detailed placement problem where the objective is to optimize (and tradeoff) total bounding box wirelength and timing. First, we view the placement of a cell as a bit-sequence which hierarchically encodes the procedure of constraining the cell to an exact location (exact row and column). Such bit sequences indicate a recursive dissection of the layout area. We argue that the search strategy indicated by the placement encoding has compelling advantages over typical ones in terms of search efficiency. Second, the branch-and-bound method with hierarchical placement encoding can inherently expose the possibly improved configurations and provide a mechanism for exploiting the abundant opportunities for tradeoffs between different design objectives. Our experiments start with the placements of 12 of the largest MCNC benchmarks from VPR, iteratively extract and release parts of the cells to larger regions (that defines the search space) and optimally (or nearly optimally) place these cells with respect to the search space. The experiments show that the wire length of the placements can be improved 11% on average with simultaneous reduction in the critical path delay of the routed placements (6.3% on average).
  • Keywords
    VLSI; circuit optimisation; encoding; integrated circuit design; tree searching; MCNC benchmark; VLSI design; bit-sequence; branch-and-bound method; hierarchical placement encoding; iterative extraction; search strategy; total bounding box wirelength optimization; Algorithm design and analysis; Computer science; Cost function; Delay; Encoding; Law; Legal factors; Optimization methods; Timing; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design, 2009. ASQED 2009. 1st Asia Symposium on
  • Conference_Location
    Kuala Lumpur
  • Print_ISBN
    978-1-4244-4952-1
  • Electronic_ISBN
    978-1-4244-4952-1
  • Type

    conf

  • DOI
    10.1109/ASQED.2009.5206249
  • Filename
    5206249