Low-Cost TMR for Fault-Tolerance on Coarse-Grained Reconfigurable Architectures

Hardware redundancy is a common method for improving the reliability of a system. The disadvantage of this approach is the hardware overhead and the additional power consumption. This contribution proposes a strategy for implementing low-cost triple modular redundancy (TMR) on coarse-grained reconfigurable architectures (CGRAs). Low-cost TMR is achieved by utilizing unused functional units (FUs) for the redundant computation of results. This is realized by combining the FUs of three processing elements in a fault-tolerant data path. Experimental results show that the proposed approach reduces area in a 8-bit architecture by 12.8% and average power consumption is decreased between 1.6 and 18.6% when compared with a fault-tolerant CGRA implemented by conventional TMR.