Platform stitching capacitors impact to high-speed differential links on non-ideal return path

This paper discusses the validity of platform stitching capacitors in facilitating high-speed differential links signal return path on non-ideal reference plane. A platform design guideline for the stitching capacitor is recommended at the end of this study. The results from this study were used to enable a huge reduction in the number of platform stitching capacitors, which scored major design wins to both Intel internal and external customers. The cost saving is estimated to be approximately $10M cost saving following this design guidelines, more cost saving are expected if proliferate to other product platforms and establish good method for future product implementation. Our study shows that stitching capacitors have neither significantly improve nor degrade differential signal integrity performance on non-ideal return path. There is no direct relationship between the stitching capacitors and the frequency characteristics of the differential links on non-ideal return path. Before concluding this study, we perform time-domain analysis in HSPICE and Lab measurement was taken on actual system board for SATA and PCIe interfaces. All the eye diagram results captured are showing similar trend between simulation and measurement.