• DocumentCode
    2996650
  • Title

    An 18-bit floating-point signal processor VLSI with an on-chip 512W dual-port RAM

  • Author

    Yamauchi, Hironori ; Kaneko, Takao ; Kobayashi, Tsutomu ; Iwata, Atsushi ; Ono, Sadayasu

  • Author_Institution
    N.T.T., Atsugi, Japan
  • Volume
    10
  • fYear
    1985
  • fDate
    31138
  • Firstpage
    204
  • Lastpage
    207
  • Abstract
    A brand-new floating-point Digital Speech Signal Processor VLSI (DSSP), intended for a wide range of applications in speech processing, is developed. For speech applications, a wide dynamic range vector operation that includes FFT and complex arithmetic is necessary in executing a highly-complicated coding algorithm that treats a large amount of windowed data collectively. To meet this requirement, the floating-point data format and hardware architecture is extensively studied. The DSSP, which is fabricated using 2.5um CMOS technology, completes almost all the floating-point operations within a 150ns machine-cycle.
  • Keywords
    Arithmetic; CMOS technology; Decision support systems; Dynamic range; Hardware; Signal processing; Signal processing algorithms; Speech coding; Speech processing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '85.
  • Type

    conf

  • DOI
    10.1109/ICASSP.1985.1168489
  • Filename
    1168489