Performance evaluation of buffered multistage interconnection networks with look-ahead contention resolution scheme

Author

Chen, C. Y Roger ; Almazyad, Abdulaziz S.

Author_Institution

Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA

Volume

2

fYear

1995

fDate

18-22 Jun 1995

Firstpage

1137

Abstract

Packet-switched multistage interconnection networks (MINs) have been widely used for parallel computer systems and digital data communication. It is well-known that the maximum throughput of an input-buffered switch is limited due to the head of line (HOL) blocking. To overcome the HOL blocking, a technique known as look-ahead contention resolution (LCR) is used. In this paper we first present an efficient model for the performance evaluation of MINs with the LCR scheme. Then we demonstrate by simulation that the proposed model offers an accurate and easy means for analyzing the LCR performance

Keywords

buffer storage; data communication; digital communication; multistage interconnection networks; packet switching; parallel architectures; buffered multistage interconnection networks; digital data communication; head of line blocking; input-buffered switch; look-ahead contention resolution scheme; maximum throughput; packet-switching; parallel computer systems; performance evaluation; simulation; Analytical models; Communication switching; Computational modeling; Computer networks; Concurrent computing; Data communication; Multiprocessor interconnection networks; Performance analysis; Switches; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, 1995. ICC '95 Seattle, 'Gateway to Globalization', 1995 IEEE International Conference on

Conference_Location

Seattle, WA

Print_ISBN

0-7803-2486-2

Type

conf

DOI

10.1109/ICC.1995.524278

Filename

524278