DocumentCode
2996694
Title
Self centering assessment of stacked CSP memory components
Author
Iyer, Satyanarayan ; Chennagiri, Gurudutt ; Akhbar, Abd Aziz Ali ; Ismail, Amran
Author_Institution
SMART Modular Technol., Inc., CA, USA
fYear
2009
fDate
15-16 July 2009
Firstpage
208
Lastpage
211
Abstract
The growth in demand for memory capacity is surpassing the pace at which memory component manufacturers are able to cost-effectively produce the next generation of monolithic memory devices. This drives the need for utilizing stacked components for memory module assemblies. The introduction of stacked CSP components, which consist of multiple layers of solder balls and is heavier than regular CSP components, requires that the processes used for assembling monolithic components be reviewed and re-optimized to suit its manufacturability and reliability. One of the characteristics to review is the self centering capability, which is an inherent and desirable property of area array devices that can largely compensate for the errors in placement of these components. The added weight of a stacked CSP component could inhibit its self centering characteristic. This paper presents a systematic approach to assess the self centering characteristics of a stacked CSP component. The heaviest available memory component was used for this evaluation. The findings of this assessment is useful in determining the capability requirements for the placement machine and to establish the inspection criteria. Based on the analysis and the results, the stacked CSP component was able to self center when misplaced by 50% along the diagonal.
Keywords
assembling; chip scale packaging; circuit optimisation; integrated logic circuits; monolithic integrated circuits; solders; monolithic component assembling; monolithic memory devices; reoptimization; self centering assessment; solder balls; stacked CSP memory component; Assembly; Chip scale packaging; Guidelines; Inspection; Manufacturing processes; Materials testing; Packaging machines; Random access memory; Semiconductor device packaging; Stacking;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design, 2009. ASQED 2009. 1st Asia Symposium on
Conference_Location
Kuala Lumpur
Print_ISBN
978-1-4244-4952-1
Electronic_ISBN
978-1-4244-4952-1
Type
conf
DOI
10.1109/ASQED.2009.5206268
Filename
5206268
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