DocumentCode :
2996886
Title :
An optimal design consideration for higher-order delta-sigma AD converter
Author :
Zhang, Yikui ; Hayahara, Etsuro ; Hirano, Satoshi ; Sakakibara, Naohito
Author_Institution :
Nagoya Inst. of Technol., Japan
fYear :
2000
fDate :
2000
Firstpage :
309
Lastpage :
312
Abstract :
In this paper me proposed an approach for obtaining optimal stable modulator coefficients which satisfy both SNR and stable input limit requirements. The empirical (3rd to 5th order) stable input limit formula is presented. Modulator examples are presented to demonstrate the use of the proposed method. The simulation results show that nearly 1-bit (6dB) resolution is improved with the proposed method. The op-amp DC-offset influence on modulator performance is also discussed
Keywords :
analogue-digital conversion; circuit noise; circuit optimisation; circuit stability; delta-sigma modulation; SNR requirements; delta-sigma A/D converter; empirical stable input limit formula; higher-order delta-sigma ADC; modulator performance; op-amp DC-offset influence; optimal design; optimal stable modulator coefficients; resolution improvement; stable input limit requirements; Autocorrelation; Gain; Operational amplifiers; Quantization; Signal design; Signal to noise ratio; Stability; Transfer functions; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on
Conference_Location :
Tianjin
Print_ISBN :
0-7803-6253-5
Type :
conf
DOI :
10.1109/APCCAS.2000.913496
Filename :
913496
Link To Document :
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