Architecture Based on Array Processors for Data-Dependent Superimposed Training Channel Estimation

Channel estimation is a challenging problem in wireless communication systems because of users mobility and limited bandwidth. A plethora of methods based on pilot assisted transmissions (PAT) have been proposed in most practical systems to overcome this problem, but with the penalty of extra bandwidth consumption for training. Channel estimation based on superimposed training (ST) has emerged as an alternative in recent years because it saves valuable bandwidth by adding a training periodic sequence to the data signal instead of multiplexing them. However, although ST and one of its variants, known as data dependent ST (DDST), have been an active research topic, only few physical implementations of such estimators have been reported to date. In this work a full-hardware architecture based on array processors (AP) for DDST channel estimation is presented and it is compared with previous approaches. The design was described using Verilog HDL and targeted in Xilinx Virtex-5 XC5VLX110T. The synthesis results showed a slices consumption of 3% and a frequency operation of the 115 MHz. A Monte Carlo simulation demonstrates that the mean square error (MSE) of the channel estimator implemented in hardware is practically the same than the one obtained with the floating-point golden model. The high performance and reduced hardware of the proposed channel estimator allows us to conclude that it can be utilized in practical DDST receivers developments.