Two-level logic minimization for low power

Author

Iman, S. ; Pedram, M.

Author_Institution

Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA

fYear

1995

fDate

5-9 Nov. 1995

Firstpage

433

Lastpage

438

Abstract

We study the problem of two-level logic minimization for low power in static CMOS circuits. We start by defining Power Prime Implicants (PPIs) which identify the set of all implicants that are sufficient and necessary for obtaining a minimum power solution. We then provide an efficient algorithm for generating the set of all PPIs of a function. The set of all PPIs is then used in a minimum covering problem to find the best power solution. The feasibility of generating the set of all PPIs and the increased complexity of solving the minimum covering problem are analyzed by deriving an upper bound on the expected number of PPIs which shows it to be linearly proportional to the number of prime implicants of the function. The results of our experiments are then used to draw conclusions on the effectiveness of low power two-level logic minimization.

Keywords

CMOS logic circuits; circuit CAD; circuit optimisation; integrated circuit design; logic CAD; logic design; minimisation of switching nets; Power Prime Implicants; low power two-level logic minimization; minimum covering problem; minimum power solution; static CMOS circuits; Boolean functions; CMOS logic circuits; Contracts; Cost function; Energy consumption; Logic circuits; Logic devices; Minimization methods; Programmable logic arrays; Programmable logic devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on

Conference_Location

San Jose, CA, USA

ISSN

1092-3152

Print_ISBN

0-8186-8200-0

Type

conf

DOI

10.1109/ICCAD.1995.480152

Filename

480152