• DocumentCode
    299704
  • Title

    Unconstrained speculative execution with predicated state buffering

  • Author

    Ando, Hideki ; Nakanishi, Chikako ; Hara, Tetsuya ; Nakaya, Masao

  • Author_Institution
    Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
  • fYear
    1995
  • fDate
    22-24 June 1995
  • Firstpage
    126
  • Lastpage
    137
  • Abstract
    Speculative execution is execution of instructions before it is known whether these instructions should be executed. Compiler-based speculative execution has the potential to achieve both a high instruction per cycle rate and high clock rate. Pure compiler-based approaches, however have greatly limited instruction scheduling due to a limited ability to handle side effects of speculative execution. Significant performance improvement is, thus, difficult in non-numerical applications. This paper proposes a new architectural mechanism, called predicating, which provides unconstrained speculative execution. Predicating removes restrictions which limit the compiler´s ability to schedule instructions. Through our hardware support, the compiler is allowed to move instructions past multiple basic block boundaries from any succeeding control path. Predicating buffers the side effects of speculative execution with its predicate, and the buffered predicate efficiently commits or squashes the side effects. The mechanism also provides a speculative exception handling scheme. The scheme, called the future condition properly postpones speculative exceptions and efficiently restarts the process. We show that our mechanism can be implemented through a modest amount of hardware with little complexity. The evaluation results show that our mechanism significantly improves performane, and achieves a 2.45x speedup over scalar machines.
  • Keywords
    computational complexity; computer architecture; exception handling; instruction sets; compiler-based approaches; instruction scheduling; performance improvement; predicated state buffering; speculative exception handling scheme; unconstrained speculative execution; Clocks; Computer aided instruction; Hardware; Laboratories; Large scale integration; Optimizing compilers; Parallel processing; Permission; Scheduling; VLIW;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture, 1995. Proceedings., 22nd Annual International Symposium on
  • Conference_Location
    Santa Margherita Ligure, Italy
  • ISSN
    1063-6897
  • Print_ISBN
    0-89791-698-0
  • Type

    conf

  • Filename
    524555