Design and Implementation of a Simplified Turbo Decoder for 3GPP2

Author

Yllescas-Calderón, Lennin C. ; Espino-Orozco, Adrian J. ; Parra-Michel, R. ; Gonzalez-Perez, Luis F.

Author_Institution

Dept. of Elec. Eng., CINVESTAV-Gdl, Zapopan, Mexico

fYear

2011

fDate

Nov. 30 2011-Dec. 2 2011

Firstpage

333

Lastpage

338

Abstract

In this paper a VLSI architecture for a configurable turbo decoder, compliant with the 3GPP2 standard is presented. A simple modification of the conventional iterative structure of a turbo decoder is presented, where one of the constituent interleavers can be eliminated, allowing an important reduction in the overall complexity of the turbo decoder with no performance degradations. Performance analysis is highlighted vis `a vis a fixed point reference model. In addition, results of the overall architecture with the sliding window approach and implemented on an Alter a device is shown.

Keywords

3G mobile communication; iterative methods; turbo codes; 3GPP2 standard; VLSI architecture; conventional iterative structure; fixed point reference model; simplified turbo decoder; Computer architecture; Decoding; Hardware; Iterative decoding; Measurement; Systematics; Turbo codes; 3GPP2; Interleaver; Turbo codes; VLSI architectures; channel coding; finite precision analysis; sliding window;

fLanguage

English

Publisher

ieee

Conference_Titel

Reconfigurable Computing and FPGAs (ReConFig), 2011 International Conference on

Conference_Location

Cancun

Print_ISBN

978-1-4577-1734-5

Type

conf

DOI

10.1109/ReConFig.2011.25

Filename

6128599