• DocumentCode
    299709
  • Title

    Speeding up irregular applications in shared-memory multiprocessors: memory binding and group prefetching

  • Author

    Zhang, Zheng ; Torrellas, Josep

  • Author_Institution
    Center for Supercomput. Res. & Dev., Illinois Univ., Urbana, IL, USA
  • fYear
    1995
  • fDate
    22-24 June 1995
  • Firstpage
    188
  • Lastpage
    199
  • Abstract
    While many parallel applications exhibit good spatial locality, other important codes in areas like graph problem-solving or CAD do not. Often, these irregular codes contain small records accessed via pointers. Consequently, while the former applications benefit from long cache lines, the latter prefer short lines. One good solution is to combine short lines with prefetching. In this way, each application can exploit the amount of spatial locality that it has. However, prefetching, if provided, should also work for the irregular codes. This paper presents a new prefetching scheme that, while usable by regular applications, is specifically targeted to irregular ones: memory binding and group prefetching. The idea is to hardware-bind and prefetch together groups of data that the programmer suggests are strongly related to each other. Examples are the different fields in a record or two records linked by a permanent pointer. This prefetching scheme, combined with short cache lines, results in a memory hierarchy design that can be exploited by both regular and irregular applications. Overall, it is better to use a system with short lines (16-32 bytes) and our prefetching than a system with long lines (128 bytes) with or without our prefetching. The former system runs 6 out of 7 splash-class applications faster. In particular, some of the most irregular applications run 25-40% faster.
  • Keywords
    cache storage; memory architecture; shared memory systems; cache lines; graph problem-solving; group prefetching; memory binding; memory hierarchy design; shared-memory multiprocessors; spatial locality; Data structures; Discrete event simulation; Integrated circuit interconnections; Permission; Prefetching; Problem-solving; Programming profession; Research and development; Tree graphs; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture, 1995. Proceedings., 22nd Annual International Symposium on
  • Conference_Location
    Santa Margherita Ligure, Italy
  • ISSN
    1063-6897
  • Print_ISBN
    0-89791-698-0
  • Type

    conf

  • Filename
    524560