PARAS: System-level concurrent partitioning and scheduling

Author

Wing Hang Wong ; Jain, R.

Author_Institution

Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA

fYear

1995

fDate

5-9 Nov. 1995

Firstpage

440

Lastpage

445

Abstract

Partitioning for the ASIC designs is examined and the interaction between high-level synthesis and partitioning is studied and incorporated in the solution. Four algorithms (called PARAS) which can exploit this interaction by solving the scheduling and partitioning problems concurrently are presented. PARAS maximizes the overall performance of the final design and considers different chip configurations and communication structures. Experiments, conducted with specifications ranging in size from few to hundreds of operations, demonstrate the success of this approach.

Keywords

application specific integrated circuits; circuit CAD; data flow graphs; high level synthesis; integrated circuit design; logic partitioning; ASIC designs; PARAS; chip configurations; communication structures; high-level synthesis; system-level partitioning; system-level scheduling; Algorithm design and analysis; Application specific integrated circuits; Clocks; Delay; High level synthesis; Job shop scheduling; Partitioning algorithms; Processor scheduling; Scheduling algorithm; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on

Conference_Location

San Jose, CA, USA

ISSN

1092-3152

Print_ISBN

0-8186-8200-0

Type

conf

DOI

10.1109/ICCAD.1995.480153

Filename

480153