General structure for base-m capacitive digital to analog converter

A general structure for capacitive digital to analog converters (CDACs) is presented in which non-binary, base-m capacitor sizing is introduced. Base-m sizing opens new trade-offs in area and INL/DNL efficiency. A base-4 (i.e., quaternary-weighted) DAC (QWDAC) is designed as an example of the proposed structure. This converter is designed and simulated after being laid out in a 0.18-μm CMOS technology at 1.8V power supply. In a typical 6-bit DAC using base-4 technique, the area reduces by a factor of three as compared to the conventional binary weighted DAC. Several Monte-Carlo simulations suggest that capacitor mismatch effect of the base-m structure is reduced owing to the smaller number of separate capacitors involved in the generation of a desired code. Moreover, the general base-m structure can be generalized to two-stage CDAC and C-2C architectures to improve the area efficiency.