Power optimization in multipliers using multi-precision combined with voltage scaling techniques

Low-power design is essential for computation-intensive systems such as digital signal processors (DSP) as well as battery-powered devices. This paper presents a novel low-power multiplier architecture, which exploits the effective dynamic range of the input data and performs a run-time multi-precision multiplication. Block-wise shutdown and voltage scaling techniques are combined to disable unused resources and adjust the supply voltage and clock frequency to reduce power consumption. This results in nearly a cubic reduction in dynamic power dissipation. Furthermore, by using modified Booth encoding scheme, partial products generating algorithm, and compression topology, our multiplier achieves both delay and power reduction. The design is synthesized using TSMC 0:18 mum standard cell library and evaluated in Synopsys design environment. Reported results show that our multiplier achieves up to 75% power reduction with less than 10% overhead in terms of silicon area.