DocumentCode
2997288
Title
Reconfigurable Designs for Networking Silicon
Author
Li, Tao ; Liu, Zhentao ; Du, Huimin ; Zhang, Lei ; Han, Jungang ; Jiang, Lin ; Dong, Qingang
Author_Institution
Coll. of Electron. Eng., Xi´´an Univ. of Posts & Telecom, Xian, China
fYear
2012
fDate
21-25 May 2012
Firstpage
294
Lastpage
299
Abstract
This paper presents a reconfigurable architecture and associated design methodology for developing networking silicon chips. The tools include most of the common traffic QoS features and low level interfaces as well as some special features for extensible design. When coupled with the design tools, this architecture provides powerful capabilities for the design of highly flexible networking silicon IP cores.
Keywords
elemental semiconductors; integrated circuit design; logic circuits; microprocessor chips; quality of service; reconfigurable architectures; silicon; Si; design tool methodology; highly flexible networking silicon IP core chip; low level interface; reconfigurable architecture; traffic QoS feature; Admission control; Generators; Pipelines; Reconfigurable architectures; Silicon; Traffic control; design automation; interface processor; networking; quality of service; reconfigurable architecture; traffic control;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2012 IEEE 26th International
Conference_Location
Shanghai
Print_ISBN
978-1-4673-0974-5
Type
conf
DOI
10.1109/IPDPSW.2012.35
Filename
6270654
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