From Instruction Traces to Specialized Reconfigurable Arrays

This paper presents an offline tool-chain which automatically extracts loops (Mega blocks) from Micro Blaze instruction traces and creates a tailored Reconfigurable Processing Unit (RPU) for those loops. The system moves loops from the CPU to the RPU transparently, at runtime, and without changing the executable binaries. The system was implemented in an FPGA and for the tested kernels measured speedups ranged between 3.9× and 18.2× for a Micro Blaze CPU without cache. We estimate speedups from 1.03× to 2.01×, when comparing to the best estimated performance achieved with a single Micro Blaze.