DocumentCode
2997356
Title
Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth
Author
Hironaka, Kazuei ; Amano, Hideharu
Author_Institution
Dept. of Inf. & Comput. Sci., Keio Univ., Yokohama, Japan
fYear
2011
fDate
Nov. 30 2011-Dec. 2 2011
Firstpage
404
Lastpage
409
Abstract
A coarse grained dynamically reconfigurable processor (CGDRP) with both Dual Vddand Dual Vth is proposed with power centric Dual Vdd and Dual Vth assignment policies. The evaluation result shows that the Vth and Vdd assignment optimization algorithm reduces 37% of total consuming power within keeping the operational frequency.
Keywords
power aware computing; reconfigurable architectures; system-on-chip; Dual Vth assignment policies; Vdd assignment optimization algorithm; Vth assignment optimization algorithm; coarse grained dynamically reconfigurable processor; dual Vdd assignment policies; dual Vth assignment policies; power centric application mapping; system-on-chips; total consuming power reduction; Arrays; Clocks; Context; Delay; Field programmable gate arrays; Optimized production technology; Switches; CGRA; DRPA; coarse grained dynamically reconfigurable device; reconfigurable device;
fLanguage
English
Publisher
ieee
Conference_Titel
Reconfigurable Computing and FPGAs (ReConFig), 2011 International Conference on
Conference_Location
Cancun
Print_ISBN
978-1-4577-1734-5
Type
conf
DOI
10.1109/ReConFig.2011.70
Filename
6128611
Link To Document