• DocumentCode
    2997393
  • Title

    An Enhanced Relocation Manager to Speedup Core Allocation in FPGA-based Reconfigurable Systems

  • Author

    Santambrogio, M.D. ; Cancare, F. ; Cattaneo, R. ; Bhandari, S. ; Sciuto, D.

  • fYear
    2012
  • fDate
    21-25 May 2012
  • Firstpage
    336
  • Lastpage
    343
  • Abstract
    Self Reconfigurable Systems are completely independent in their management, thus they have the need to internally host reconfiguration management functionalities, such as core allocation, and to store or be able to autonomously obtain configuration bit streams when needed. Within this scenario, the final system also needs to be able to autonomously perform choices relative to its internal management during computation, this requires, in particular, an internal solution for core allocation management, which includes maintaining information on the reconfigurable fabric state and being able to choose where to place new cores upon their arrival. We refer to these two aspects with the terms Empty Space Management and Online Placement Policy and to the global problem with the term Online Core Allocation Management. This paper presents a solution able to combine the online placement of cores with the runtime bit streams relocation to implement a complete solution that can be used in conjunction with the runtime self reconfiguration. The validation phase presents the results obtained in placement management and relocation, compared to the results obtained by the state of art solutions to this problem.
  • Keywords
    field programmable gate arrays; reconfigurable architectures; resource allocation; storage allocation; FPGA-based reconfigurable system; configuration bitstreams; empty space management; enhanced relocation manager; global problem; online core allocation management; online placement policy; reconfigurable fabric state; reconfiguration management functionalities; runtime bitstreams relocation; runtime self-reconfiguration; self-reconfigurable systems; speedup core allocation; validation phase; Field programmable gate arrays; Hardware; Payloads; Registers; Resource management; Schedules; Tiles;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2012 IEEE 26th International
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-1-4673-0974-5
  • Type

    conf

  • DOI
    10.1109/IPDPSW.2012.41
  • Filename
    6270660