A parser processor for MPEG-2 audio and AC-3 decoding

Author

Lee, Seokjun ; Sung, Wonyong

Author_Institution

Dept. of Electr. Eng., Seoul Nat. Univ., South Korea

Volume

4

fYear

1997

fDate

9-12 Jun 1997

Firstpage

2621

Abstract

We developed a parser processor for the efficient implementation of logic intensive operations needed for the pre-processing of MPEG-2 audio and AC-3 bit streams. The proposed parser processor requires a relatively small chip area, while it can support multiple audio standards by programming. The complexity of the parser processor is below 10,000 gates and the memory requirement is about 5 kbytes including the instruction memory, internal RAM and parameter ROM. The operating speed is 25 MHz, which can accommodate the maximum bit rate of MPEG-2 Audio and AC-3. The hardware complexity and the execution speed of the developed processor are compared with those of a programmable digital signal processor based design and a dedicated hardware chip

Keywords

audio coding; decoding; digital signal processing chips; grammars; 25 MHz; 5 kbyte; AC-3 decoding; MPEG-2 audio; bit steam processing; dedicated hardware chip; digital audio standard; instruction memory; internal RAM; logic operation; parameter ROM; parser processor; programmable digital signal processor; Bit rate; Decoding; Digital signal processors; Hardware; Logic programming; Process design; Random access memory; Read only memory; Read-write memory; Streaming media;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on

Print_ISBN

0-7803-3583-X

Type

conf

DOI

10.1109/ISCAS.1997.612862

Filename

612862