Title :
Cool-Fetch: a compiler-enabled IPC estimation based framework for energy reduction
Author :
Unsal, Osman S. ; Koren, Israel ; Khrishna, C.M. ; Moritz, Csaba Andras
Author_Institution :
Intel Barcelona Res. Center, Intel Labs UPC, Barcelona, Spain
Abstract :
With power consumption becoming an increasingly important factor, it is necessary to reevaluate traditional, power-intensive, architectural techniques and their relative performance benefits. We believe that combined architecture-compiler efforts open up new and efficient ways to retain the performance benefits of modern architectures while addressing their power impact. In this paper, we present Cool-Fetch, an architecture compiler based approach to reduce energy consumption in the processor. While we mainly target the fetch unit, an important side-effect of our approach is that we obtain energy savings in many other parts of the processor. The explanation is that the fetch unit often runs substantially ahead of execution, bringing in instructions to different stages in the processor that may never be executed. We have found that although the degree of instruction level parallelism (ILP) of a program tends to vary over time, it can be statically estimated by the compiler. Our instructions per clock (IPC) estimation scheme uses monotonic dataflow analysis and simple heuristics, to guide a fetch-throttling mechanism. We develop the necessary architecture support and include its power overhead. Using Mediabench and SPEC2000 applications, we obtain up to 15% total energy savings in the processor with generally little performance degradation. We also provide a comparison of Cool-Fetch with previously proposed hardware-only dynamic fetch-throttling schemes.
Keywords :
computer architecture; data flow analysis; instruction sets; microprocessor chips; parallel programming; parallelising compilers; power consumption; Cool-Fetch; Mediabench application; Our instructions per clock; SPEC2000 application; architecture compiler; compiler-enabled IPC estimation; energy reduction; energy savings; fetch unit; fetch-throttling mechanism; instruction level parallelism; monotonic dataflow analysis; power consumption; Clocks; Data analysis; Degradation; Energy consumption; Energy dissipation; Microarchitecture; Out of order; Parallel processing; Program processors; Testing;
Conference_Titel :
Interaction between Compilers and Computer Architectures, 2004. INTERACT-8 2004. Eighth Workshop on
Print_ISBN :
0-7695-2061-8
DOI :
10.1109/INTERA.2004.1299509