A power efficient multi-level output all digital LDO with fast settling time and built in self calibration for DVFS and multi-VDD applications

This paper describes a new kind of All Digital Low Dropout Regulator (ADLDO) which is Multiple Reference All Digital Low Dropout Regulator (MRADLDO) with 98.1% current efficiency and 100mA maximum load current. The proposed LDO includes several reference voltages to apply in the multi VDD core circuits, and it is appropriate for Dynamic Voltage and Frequency Scaling (DVFS) technique in order to control the delay and speed of the circuit. Furthermore, self calibration by parallel loading last data reference into the LDO shift register is implemented for the sake of decreasing the steady-state time. Subsequently, MRADLDO is applied in ARM1176JZF-S processor supply applying four levels of voltage: high level (1.21V), medium level (1.14V), low level (0.99V) and sleep mode (0V). Moreover, in order to decrease the setup time for changing the output voltage (Vout) while reference voltage (Vref) is changed, a simple memory which saves and loads LDO shift register initial data is proposed.