VLSI Architecture for an adaptive equalizer in ISDN line termination

VLSI architecture for an Adaptive equalizer needed to provide digital subscriber line transmission at hundreds of kbits/s is described. A wide AGC dynamic range, and quick adjustment of the filter coefficients are required for precise adaptive equalization. Considering the advances in VLSI technology, a single-chip multi-processor VLSI, composed of a high-speed filtering processor, control processors, analog-to-digital converter, and digital phase-locked loop (DPLL) is proposed. All processors are synchronized by the internal DPLL. The performance of the key components, developed using 1.5µm CMOS technology, shows that a fully integrated CMOS VLSI capable of implementing all functions of an adaptive equalizer is entirely feasible.