DGECS: Description Generator for Evolved Circuits Synthesis

Evolvable Hardware (EHW) is an approach to the creation of hardware circuits based on a goal-oriented evolutionary process inspired by natural evolution. This approach allows the exploration of a very large design search space, ideally enabling to find solutions that are better in terms of resource requirements, accuracy or timing performance, with respect to traditional design methods. To exploit this approach, it must be possible to port the evolved circuits to custom designs, however, in FPGA-based EHW systems (and, in particular, in the HERA project), the configuration bit stream for an evolved circuit is specific to the evolutionary platform and it cannot be ported to a different architecture. This paper expands the HERA framework with a tool able to export hardware circuits evolved within the HERA framework to an IP-core reusable in any PLB-based custom design. DGECS (Description Generator for Evolved Circuits Synthesis) permits to export evolved circuits to a VHDL description which can be then synthesized and plugged into a custom PLB architecture. Experimental results provide evidence that DGECS allows to correctly export evolved circuits, moreover, it enables to save resources thanks to the optimizations introduced by the synthesis flow it relies on.