Title :
Extraction of geometry-related interconnect variation based on parasitic capacitance data
Author :
Li-Jie Sun ; Jia Cheng ; Zheng Ren ; Gan-Bing Shang ; Shao-Jian Hu ; Shou-Mian Chen ; Yu-Hang Zhao ; Long Zhang ; Xiao-Jin Li ; Yan-Ling Shi
Author_Institution :
Key Lab. of Polar Mater. & Devices, East China Normal Univ., Shanghai, China
Abstract :
A new interconnect parasitic extraction flow considering geometry-related variation has been proposed in this letter. The 42 interconnect capacitance loads were fabricated by 55-nm process technology and measured to characterize geometric variation. According to the new extraction flow, interconnect technology file (ITF) has been optimized and established. As a result, both extracted error by layout parasitic extraction tool and simulated error by field solver have been improved obviously with this optimized ITF. Meanwhile, an on-chip interconnect test technique with nonoverlapping signal generation circuitry based on charge-induced-injection error-free charge-based capacitance measurement has been designed in this letter to simplify the test procedure.
Keywords :
capacitance measurement; charge-coupled devices; geometry; integrated circuit interconnections; integrated circuit testing; signal generators; ITF; charge-induced-injection error-free charge-based capacitance measurement; geometry-related interconnect variation extraction flow; interconnect parasitic extraction; interconnect technology file; layout parasitic extraction tool; nonoverlapping signal generation circuitry; on-chip interconnect test technique; parasitic capacitance data; size 55 nm; Data mining; Integrated circuit interconnections; Layout; Metals; Parasitic capacitance; System-on-chip; Geometric-related variation; charge-induced-injection error-free charge-based capacitance measurement (CIEF CBCM); interconnect parasitic extraction; non-overlapping signal generation circuitry;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2014.2344173
