Title :
A fast cycle-based approach for synthesizable RT level VHDL simulation
Author :
Ghasemzadeh, Lily ; Navabi, Zainalabedin
Author_Institution :
Dept. of Electron. & Comput. Eng., Tehran Univ., Iran
Abstract :
In this paper a cycle-based RT level simulation method is being discussed. Issues treated include feedback detection, component ordering and component extraction from behavioral VHDL descriptions
Keywords :
circuit feedback; hardware description languages; high level synthesis; logic simulation; VHDL simulation; asynchronous feedback loops; component extraction; component ordering; cycle-based RT level; feedback detection; logic design; synthesizable RT level; Circuit simulation; Clocks; Computational modeling; Discrete event simulation; Feedback loop; Flip-flops; Hardware; Logic design; Scheduling algorithm; Timing;
Conference_Titel :
Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on
Conference_Location :
Tianjin
Print_ISBN :
0-7803-6253-5
DOI :
10.1109/APCCAS.2000.913540
