Fabrication of CMOS circuits using non-etchback SOG processing for dielectric planarization

Author

Chung, Henry W M ; Gupta, Satish K. ; Baldwin, Teresa A.

Author_Institution

Signetics Corp., Sunnyvale, CA, USA

fYear

1989

fDate

12-13 Jun 1989

Firstpage

373

Lastpage

381

Abstract

Planarization of interlevel dielectrics by nonetchback spin-on glass (SOG) techniques requires the use of a dense, inorganic SOG with good dielectric characteristics. The authors have evaluated two recently developed phosphosilicate-type SOG materials, Accuglass P-114 and P-114A, for use in nonetchback processing. Both materials were successfully applied to the fabrication of 1.2-μm CMOS ASIC circuits. Extensive reliability tests, including thermal stressing of via chains, DHTL, PPOT, and THBS were performed at the wafer level and on packaged parts fabricated with P-114. The very favorable results confirm the viability of the nonetchback process used

Keywords

CMOS integrated circuits; VLSI; application specific integrated circuits; dielectric thin films; glass; materials testing; metallisation; reliability; 1.2 micron; Accuglass P-114; CMOS ASIC circuits; CMOS circuits; DHTL; P2O5-SiO2; PPOT; PSG; THBS; dielectric characteristics; dielectric planarization; inorganic SOG; interlevel dielectrics; nonetchback processing; nonetchback spin-on glass; packaged parts; reliability tests; thermal stressing; via chains; viability; wafer level; Application specific integrated circuits; CMOS process; Circuit testing; DH-HEMTs; Dielectric materials; Fabrication; Glass; Performance evaluation; Planarization; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Multilevel Interconnection Conference, 1989. Proceedings., Sixth International IEEE

Conference_Location

Santa Clara, CA

Type

conf

DOI

10.1109/VMIC.1989.77997

Filename

77997