Fabrication of CMOS circuits using non-etchback SOG processing for dielectric planarization

Planarization of interlevel dielectrics by nonetchback spin-on glass (SOG) techniques requires the use of a dense, inorganic SOG with good dielectric characteristics. The authors have evaluated two recently developed phosphosilicate-type SOG materials, Accuglass P-114 and P-114A, for use in nonetchback processing. Both materials were successfully applied to the fabrication of 1.2-μm CMOS ASIC circuits. Extensive reliability tests, including thermal stressing of via chains, DHTL, PPOT, and THBS were performed at the wafer level and on packaged parts fabricated with P-114. The very favorable results confirm the viability of the nonetchback process used