DocumentCode
2998038
Title
Low power CMOS circuits with clocked power
Author
Wu, Xunwei ; Pedram, Massoud
Author_Institution
Inst. of Circuits & Syst., Ningbo Univ., Ningbo, China
fYear
2000
fDate
2000
Firstpage
513
Lastpage
516
Abstract
In view of changing the type of energy conversion in CMOS circuits, the authors investigate low power CMOS circuit design which adopts a gradually changing power clock. They discuss the algebraic expressions and the corresponding properties of clocked power signals. A clocked CMOS gate structure is presented and the clocked combinational circuit design is analyzed. The PSPICE simulations demonstrate the low power characteristic of clocked CMOS circuits using trapezoidal power-clock
Keywords
CMOS logic circuits; combinational circuits; integrated circuit design; logic design; low-power electronics; sequential circuits; timing; PSPICE simulations; algebraic expressions; clocked CMOS gate structure; clocked combinational circuit design; clocked power; clocked power signals; gradually changing power clock; low power CMOS circuit design; low power characteristic; trapezoidal power-clock; CMOS logic circuits; Capacitance; Circuit synthesis; Clocks; Energy conversion; Energy dissipation; Magnetic fields; Power supplies; Resistance heating; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on
Conference_Location
Tianjin
Print_ISBN
0-7803-6253-5
Type
conf
DOI
10.1109/APCCAS.2000.913549
Filename
913549
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