• DocumentCode
    2998172
  • Title

    Assignment-space exploration approach to testable data-path synthesis for minimizing partial scan registers

  • Author

    Kaneko, Mineo ; Shimizu, Yuuichiro ; Tayu, Satoshi

  • Author_Institution
    Sch. of Inf. Sci, Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    540
  • Lastpage
    543
  • Abstract
    In this paper, we present an assignment-driven approach to data-path synthesis for area-efficient partial scan testability. The method basically adopts branch-and-bound strategy for exploring assignment solution space as a backbone task, and the lower bound estimates of the scheduling length, the number of scan registers and area are used for pruning. Algorithms for lower bound estimation of the number of scan registers and selection of scan registers as a leaf task are mainly demonstrated in this paper, while the assignment-driven scheduling is relegated to a previous paper
  • Keywords
    VLSI; design for testability; high level synthesis; minimisation of switching nets; scheduling; sequential circuits; tree searching; assignment-space exploration approach; backbone task; branch-and-bound strategy; leaf task; lower bound estimates; lower bound estimation; partial scan registers; pruning; scheduling length; testable data-path synthesis; High level synthesis; Information science; Merging; Performance evaluation; Scheduling; Sequential analysis; Space exploration; Space technology; Synchronous generators; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2000. IEEE APCCAS 2000. The 2000 IEEE Asia-Pacific Conference on
  • Conference_Location
    Tianjin
  • Print_ISBN
    0-7803-6253-5
  • Type

    conf

  • DOI
    10.1109/APCCAS.2000.913556
  • Filename
    913556